This invention relates to an improved method of the use of transfer molding for encapsulating and underfilling integrated circuit chips attached to substrates to result in integrated circuit packages. It also relates to the mold and apparatus used in the improved method and the resultant integrated circuit assemblies.
An integrated circuit chip assembly generally comprises an integrated circuit chip attached to a substrate, typically a chip carrier or a circuit board. The most commonly used integrated circuit chip is composed primarily of silicon having a coefficient of thermal expansion of about 2 to 4 ppm/xc2x0C. The chip carrier or circuit board is typically composed of either a ceramic material having a coefficient of thermal expansion of about 6 ppm/xc2x0 C., or an organic material, possibly reinforced with organic or inorganic particles or fibers, having a coefficient of thermal expansion in the range of about 6 to 50 ppm/xc2x0 C. One technique well known in the art for interconnecting integrated circuit chips and substrates is flip chip bonding. In flip chip bonding, a pattern of solder balls is formed on the active surface of the integrated circuit chip, allowing complete or partial population of the active surface with interconnection sites. The solder balls which typically have a diameter of about 0.002 to 0.006 inches, are deposited on solder wettable terminals on the active surface of the integrated circuit chip forming a pattern. A matching footprint of solder wettable terminals is provided on the substrate. The integrated circuit chip is placed in alignment with the substrate and the chip to substrate connections are formed by reflowing the solder balls. Flip chip bonding can be used to attach integrated circuit chips to chip carriers or directly to printed circuit boards. The terminals located on the side of the substrate facing the integrated circuit chip are in turn interconnected to connecting balls or pins on the opposite side of the substrate in a well known manner in order to facilitate the external connection of the assembly to contacts or terminals on, for example, a circuit board.
A feature of established practices in the integrated circuit industry, provides that the substrate with the attached integrated circuit chip are formed into a package by encapsulating the assembly into a unitary package. This provides physical and environmental protection for the delicate integrated circuit chip including isolating the integrated circuit chip and the interconnections from moisture. It also provides firm bonding between the integrated circuit chip and the substrate to thereby prevent relative movement between them and the potential disruption of the interconnections.
During operation of an integrated circuit chip assembly, cyclic temperature excursions cause the substrate and the integrated circuit chip to expand and contract. Since the substrate and the integrated circuit chip have different coefficients of thermal expansion, they expand and contract at different rates, possibly causing the solder ball connections to weaken or even crack as a result of fatigue. To remedy this situation, it is common industry practice to reinforce the solder ball connections with a thermally curable polymer material known in the art as an underfill encapsulant.
Underfill encapsulants have been widely used to improve the fatigue life of integrated circuit chip assemblies consisting of an integrated circuit chip of the flip chip variety attached to a substrate made of alumina ceramic material having a coefficient of thermal expansion of about 6 ppm/xc2x0C. More recently, integrated circuit assemblies having an integrated circuit chip of the flip chip type attached to a substrate made of a reinforced organic material with a composite coefficient of thermal expansion of about 20 ppm/xc2x0 C. have been manufactured.
During the packaging of the integrated circuit attached to the substrate, the underfill encapsulation process is typically accomplished by dispensing the liquid encapsulant at one or more points along the periphery of the integrated circuit chip. The encapsulant is drawn into the gap between the integrated circuit chip and the substrate by capillary forces, substantially filling the gap and forming a fillet around the perimeter of the integrated circuit chip. An example of such an underfilling method is described in U.S. Pat. No. 5,817,545, entitled xe2x80x9cPressurized Underfill Encapsulation Of Integrated Circuitsxe2x80x9d, which issued Oct. 6, 1998.
The diameter of the filler particles in the encapsulant are sized to be smaller than the height of the gap so as not to restrict flow. Typical encapsulant formulations have a viscosity of about 10 Pa-s at the dispense temperature. After the encapsulant has flowed into the gap, it is cured in an oven at an elevated temperature.
Cured encapsulants typically have coefficients of thermal expansion in the range of about 20 to 40 ppm/xc2x0C., and a Young""s Modulus of about 1 to 3 GPa, depending on the filler content and the polymer chemistry. It may be desirable in some cases to further alter the cured properties of the encapsulant, however, the requirement that the encapsulant have low viscosity in the uncured state severely restricts the formulation options. For example, the addition of more ceramic filler would lower the resulting coefficient of thermal expansion, but increase the uncured viscosity.
Known in the art are methods for encapsulation of a flip chip package wherein a package body is formed around the perimeter of the flip chip in a two step process. First the integrated circuit chip is underfilled as previously described for the packaging, and then a package body is formed around the perimeter of the integrated circuit chip using a molding process. In yet another known method, additional reinforcement is achieved by encapsulating both faces of the flip chip and its perimeter in a single step. In this technique, the gap between the integrated circuit chip and the substrate has been substantially eliminated by forming a hole in the substrate that comprises a significant portion of the active area of the integrated circuit chip. This approach essentially eliminates the small gap typical of a conventional integrated circuit chip to substrate interconnection, but has the drawback of limiting the active area of the integrated circuit chip that can be used for forming interconnections because only the perimeter of the integrated circuit chip can be used. Examples of descriptions of injection encapsulation making use of an opening in the substrate below the integrated circuit chip in order to encapsulate the interconnections are described in U.S. Pat. No. 6,081,997, entitled xe2x80x9cSystem and Method For Packaging An Integrated Circuit Using Encapsulant Injectionxe2x80x9d, which issued Jul. 4, 2000 and U.S. Pat. No. 5,981,312, entitled xe2x80x9cMethod For Injection Molded Flip Chip Encapsulationxe2x80x9d, which issued Nov. 9, 1999.
Another example of attempts to improve the encapsulation of integrated circuit packages is described in European patent application EP1075022, entitled xe2x80x9cOffset Edges Mold For Plastic Packaging Of Integrated Semiconductor Devicesxe2x80x9d, which was published Feb. 7, 2001. In this application the description includes causing and directing the flow of plastic resin to the more restricted areas into the depressed central areas of the mold below where the device is located in a cavity as well as the upper part of the cavity above the device.
Notwithstanding the use of known underfill encapsulation techniques, fatigue life of an integrated circuit chip assembly may be shorter when the solder interconnections are made to organic substrates as opposed to ceramic substrates, owing to the greater mismatch in thermal expansion. Together with the limitations imposed on formulation options by the low viscosity requirement, improvements in encapsulation techniques and the mechanical reinforcement of integrated circuit chip interconnections are still required.
It is an object of the present invention to provide improved techniques resulting in a more uniform and controlled flow of encapsulant for more effectively removing air and minimizing moisture entrapment sites from the vicinity of a integrated circuit chip on a substrate during encapsulation.
It is another object of the present invention to provide a method for more efficiently and completely encapsulating an integrated circuit package than is presently available.
It is also an object of the present invention to provide a novel mold and apparatus for use in carrying out the aforementioned method as well as a resulting uniquely configured integrated circuit package product.
According to one aspect of the invention there is provided a method for encapsulating and underfilling an integrated circuit chip assembly comprising the steps of providing an integrated circuit assembly including an integrated circuit chip mounted on a substrate in a standoff relationship, providing a mold having a first cavity, a second cavity and at least one channel interconnecting the first and second cavities such that the at least one channel connects to the first cavity at least at one location, positioning the mold over the integrated circuit assembly such that the integrated circuit chip is located in the first cavity, applying a clamp force to hold the substrate against the mold, and injecting encapsulant into the first cavity of the mold remotely spaced from the point of connection of the at least one channel to the cavity, such that encapsulant flows around and underneath the integrated circuit chip and through the channel into the second cavity to thereby underfill and encapsulate the integrated circuit assembly.
According to another aspect of the invention there is provided a mold for encapsulating and underfilling an integrated circuit chip assembly. The mold comprises a first mold portion having first and second cavities and a channel interconnecting the first and second cavities, the first cavity being adapted for enclosing the integrated circuit chip on the substrate, a second mold portion, the first and second mold portions being adapted to clamp the substrate between the first and second portions with the integrated circuit chip located within the first cavity, a vent for exhausting air from the first cavity, and injecting structure for injecting encapsulant into the first cavity of the first mold portion at a location in the first portion remote from the point of connection of the channel to the first cavity, such that encapsulant flows around and underneath the integrated circuit chip and through the channel into the second cavity to thereby underfill and encapsulate the integrated circuit assembly.
According to another aspect of the invention there is provided an apparatus for encapsulating and underfilling an integrated circuit chip assembly including an integrated circuit chip mounted on a substrate in a standoff relationship. The apparatus comprises a mold having a first portion and a second portion, the first portion having first and second cavities and at least one channel interconnecting the first and second cavities, said first cavity being adapted to enclose the integrated circuit chip on the substrate, a vent for exhausting air from the first cavity, and injecting structure for injecting encapsulant into the first cavity of the first portion at a location in the first portion remote from the point of connection of the channel to the first cavity, such that encapsulant flows around and underneath the integrated circuit chip and through the channel into the second cavity to thereby underfill and encapsulate the integrated circuit assembly.
According to yet another aspect of the invention there is provided an integrated circuit package which comprises an integrated circuit chip mounted on a top surface of a substrate in a standoff relationship, an encapsulant body adhering to the top surface of the substrate, encapsulating the chip and filling the standoff space between the chip and substrate, and at least one elongated encapsulant channel adhering to the top surface of the substrate and extending outwardly from the encapsulated chip.
The foregoing, together with other features and advantages of the present invention, will become more apparent when referring to the following specification of preferred embodiments of the invention and the accompanying drawings.